In my Computer Organization course, there are 2 projects of implementing MIPS CPUs in Verilog, one single-cycle and the other pipeline. Whenever I learn a new programming language or whatsoever, I google the style of the language first… (code mysophobia? lol) Anyway, here are some Verilog RTL style guidelines I find important and useful from Chapter 5 of the famous SoC book Reuse Methodology Manual for System-on-a-Chip Designs.

Verilog RTL Style Guide

  • All modules use output reg .

  • Use parameter or `define for immediates.

  • Lowercase with underscores for signal, variable and port names; uppercase for constants and user-defined types.

  • For modules with multiple parameters, use short names instead of long describable names.

  • Use same naming convention for all clock signals, e.g., clk, clk1… and same name for signals driven by same clock drivers.

  • Use different suffix for different state variables: <name>_cs for current state and <name>_ns for next state.

  • Order of declaring ports in modules:

    • Inputs
      • Clocks
      • Resets
      • Enables
      • Other control signals
      • Data and address lines
    • Outputs
      • Clocks
      • Resets
      • Enables
      • Other control signals
      • Data
  • Use functions instead of rewriting the same code. Write reusable functions if possible.

  • Store constants and parameters in separate files, e.g., DesignName_constants.v, DesignName_parameters.v.

  • Reset signal should clear all regs; it is not a input of FSMs.

  • Naming like rst_a for asynchronous reset and rst for synchronous reset.

  • Initialize outputs to avoid latches.

  • Always use unblocked assignment <= inside always @(posedge clk) blocks.

  • Avoid latencies in RTL code.

  • Put relevant comb logics in same modules.